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Product Specification
PE43503
Page 7 of 11
Document No. 70-0252-05  www.psemi.com
?008-2009 Peregrine Semiconductor Corp. All rights reserved.
Table 11. Parallel and Direct Interface AC
Table 10. Serial Interface AC Characteristics
V
DD
 = 3.3 or 5.0 V, -40?C < T
A
 < 85?C, unless otherwise specified
V
DD
 = 3.3 or 5.0 V, -40?C < T
A
 < 85?C, unless otherwise specified
Figure 15. Serial Timing Diagram
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
Symbol 
Parameter 
Min    Max    Unit 
F
CLK
 
Serial clock frequency
-
10
MHz
T
CLKH
 
Serial clock HIGH time
30
-
ns
T
CLKL
 
Serial clock LOW time
30
-
ns
T
LESU
 
Last serial clock rising edge
setup time to Latch Enable
rising edge
10
-
ns
T
LEPW
 
Latch Enable min. pulse width
30
-
ns
T
SISU
 
Serial data setup time
10
-
ns
T
SIH
 
Serial data hold time
10
-
ns
T
DISU
 
Parallel data setup time
100
-
ns
T
DIH
 
Parallel data hold time
100
-
ns
T
ASU
 
Address setup time
100
-
ns
T
AH
 
Address hold time
100
-
ns
T
PSSU
 
Parallel/Serial setup time
100
-
ns
T
PSH
 
Parallel/Serial hold time
100
-
ns
T
PD
 
Digital register delay (internal)
-
10
ns
Symbol
Parameter
Min    Max    Unit
T
LEPW
 
Latch Enable minimum
pulse width
30
-
ns
T
DISU
 
Parallel data setup time
100
-
ns
T
DIH
 
Parallel data hold time
100
-
ns
T
PSSU
 
Parallel/Serial setup time
100
-
ns
T
PSIH
 
Parallel/Serial hold time
100
-
ns
T
PD
 
Digital register delay
(internal)
-
10
ns
T
DIPD
 
Digital register delay
(internal, direct mode only)
-
5
ns
Characteristics
VALID
T
DISU
T
DIH
DI[6:2]
LE
P/S
T
PSSU
T
PSIH
T
LEPW
VALID
DO[6:2]
T
DIPD
T
PD
D[0], D[1] and D[7] must be set to logic low
Bits can either be set to logic high or logic low
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[7]
T
SISU
T
CLKL
T
LEPW
T
SIH
T
CLKH
SI
CLK
LE
P/S
T
LESU
T
PSSU
T
PSIH
VALID
T
DISU
T
PD
T
DIH
D[6]
DI[6:2]
DO[6:0]
-
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